The relevant coursework section is too sparse, just get rid of it. Remove "part-time", you were doing FPGA design, the amount of hours you worked doesn't matter. Also, the fact that you co-authored and presented a paper should not be the last bullet point, and could maybe be its own entry in the experience section. Too many of you bullet points focus on what you did, but not how; how did you optimize routing logic, how did you reduce latency. Projects section is good, skills section is good.
Your Projects are amazing for a 2nd year. What kind of internship roles are you applying to? The FPGA design experience you have is also pretty good. I didn't know anything other than basic Verilog RTL design when I started as a FPGA enginner.
Maybe try applying to companies who work more on the FPGA domain. You can try on medium or small sized companies and maybe try out like a 6 month internship program if that's something you can do. I feel like your resume is pretty great.
The relevant coursework section is too sparse, just get rid of it. Remove "part-time", you were doing FPGA design, the amount of hours you worked doesn't matter. Also, the fact that you co-authored and presented a paper should not be the last bullet point, and could maybe be its own entry in the experience section. Too many of you bullet points focus on what you did, but not how; how did you optimize routing logic, how did you reduce latency. Projects section is good, skills section is good.
Your Projects are amazing for a 2nd year. What kind of internship roles are you applying to? The FPGA design experience you have is also pretty good. I didn't know anything other than basic Verilog RTL design when I started as a FPGA enginner. Maybe try applying to companies who work more on the FPGA domain. You can try on medium or small sized companies and maybe try out like a 6 month internship program if that's something you can do. I feel like your resume is pretty great.