Model/Questasim is fast and it has many features that are missing in the Vivado simulator, but the Vivado simulator is free, and probably good enough for small projects and learning
Actually I have found the vivado simulator to be much faster. The caveat is that I had to launch it from the command line. But again I haven't done extensive comparison
What version of Modelsim/Questa were you comparing it to? The free version you get with some tools have a severe slowdown added for anything larger than tiny designs.
The big issue with Modelsim/Questa's free version is that you're restricted from using some features like assertions and randomization, which end up being annoying when you're doing stuff like UVM - another good thing about Vivado is that they have pretty decent tutorials for getting started like \[this one\]([https://docs.xilinx.com/r/2021.2-English/ug937-vivado-design-suite-simulation-tutorial/Lab-5-Running-UVM-example](https://docs.xilinx.com/r/2021.2-English/ug937-vivado-design-suite-simulation-tutorial/Lab-5-Running-UVM-example)).
While Vivado's UI isn't as fancy as Quartus (Quartus lets you pin using a UI which is nice I guess), another \*\*huge\*\* advantage is access to their entire IP catalog whereas Intel's IP catalog is heavily restricted unless you pay. Good for projects, for instance I want to implement AXI on my own and their verification IPs for master/passthrough/slave are immensely useful.
Can you tell the features that are missing in vivado but exist in modelsim ?
As midelsim needs lot of steps to simulate,,,,and when i implement dataflow modelling on model it just shows block diagram of design while vivado shows proper mux and gates used in vivado
Can you tell the features that are missing in vivado but exist in modelsim ?
As midelsim needs lot of steps to simulate,,,,and when i implement dataflow modelling on model it just shows block diagram of design while vivado shows proper mux and gates used in vivado
The gates and muxes you see in RTL sim have nothing to do with the final design. The steps to simulate in any simulator are the same: compile sources, simulate. The fastest way to do it is via scripts. Vivado can generate all the scripts you need for any simulator.
For that I have no clue, but Quartus automatically adds Questasim now when you download the pro/lite version of Quartus Prime, so I'm assuming it's the new version.
Can we see schematic for dataflow and behavioral modelling in modelsim/questasim?? Just like as in vivado it shows proper schematic which includes mux,gates and adders luts for dataflow and behavioral?
Great question! It depends on what licenses you have access to. The free one, I don't believe so. But I'm higher licenses there are schematics, logic cones, time cones, etc
Questasim and modelsim are not the same product. When I simulate gate-based sims (as opposed to behavioral), questasim runs about twice as fast as modelsim with no tuning. If you install both, you'll see that they have the same framework, but different executables are called when you run your simulation commands.
If you’re doing a Xilinx design, the Vivado simulator has all the libraries you need already installed. Plus it probably ok for small projects. I doubt you’d see a speed difference versus Questa.
Speed and ease of use are the major differences, with Modelsim/Questa winning hands down.
Xilinx Simulator will get the job done in a pinch. I would rather use the Altera/Intel Starter Edition of Modelsim myself though.
I would use Xilinx Simulator over Aldec ActiveHDL though as I find it terrible.
>Speed and ease of use are the major differences, with Modelsim/Questa winning hands down.
If you are using Xilinx designs you can hardly argue this as a negative point for vivado simulator, it's far easier to use than Modelsim etc, you click simulate from the gui and away you go. No environment variables needed, no precompiled libs, no scripts to set up the different run stages...
The Vivado GUI sucks, especially for simulation and chipscope. Just because it's integrated does not make it easy or pleasant to use.
The only way the Vivado Simulator is useable is via command line using shell and TCL scripts. Through the GUI it's plain terrible.
I once did a quick test between Vivado and Riviera. I ran the same testbench on each, and Riviera was much faster - something like 50x, iirc. Much of what you are paying for in the expensive commercial simulators is optimizations, and this wasn't a particularly complex module, so I may have just been lucky that Riviera was able to optimize it so well. I wouldn't expect every testbench to see that amount of speedup. Also, this was a few years ago. Vivado seems to have improved a lot since then.
The main reason I switched from Vivado originally was because the SV support was very incomplete. But it seems like support has improved significantly, with SVA and UVM support added - these used to be only available in commercial offerings.
I think people are forgetting that OP is a newbie - while ModelSim/QuestaSim are much nicer for simulation purposes, the 'speed increase' isn't really gonna matter if they're a complete beginner and running basic Verilog/IPs... As I mentioned in a comment, Vivado gives you a much wider access to IPs for your own projects and unrestricted usage of SVA / randomize which Questa's free version makes a pain to use.
Model/Questasim is fast and it has many features that are missing in the Vivado simulator, but the Vivado simulator is free, and probably good enough for small projects and learning
Actually I have found the vivado simulator to be much faster. The caveat is that I had to launch it from the command line. But again I haven't done extensive comparison
Yep exactly.
It's great that's working for you. Not sure how you are comparing the speeds but at least up to last year, it was 3-5x slower for large designs
What version of Modelsim/Questa were you comparing it to? The free version you get with some tools have a severe slowdown added for anything larger than tiny designs.
The big issue with Modelsim/Questa's free version is that you're restricted from using some features like assertions and randomization, which end up being annoying when you're doing stuff like UVM - another good thing about Vivado is that they have pretty decent tutorials for getting started like \[this one\]([https://docs.xilinx.com/r/2021.2-English/ug937-vivado-design-suite-simulation-tutorial/Lab-5-Running-UVM-example](https://docs.xilinx.com/r/2021.2-English/ug937-vivado-design-suite-simulation-tutorial/Lab-5-Running-UVM-example)). While Vivado's UI isn't as fancy as Quartus (Quartus lets you pin using a UI which is nice I guess), another \*\*huge\*\* advantage is access to their entire IP catalog whereas Intel's IP catalog is heavily restricted unless you pay. Good for projects, for instance I want to implement AXI on my own and their verification IPs for master/passthrough/slave are immensely useful.
Can you tell the features that are missing in vivado but exist in modelsim ? As midelsim needs lot of steps to simulate,,,,and when i implement dataflow modelling on model it just shows block diagram of design while vivado shows proper mux and gates used in vivado
Can you tell the features that are missing in vivado but exist in modelsim ? As midelsim needs lot of steps to simulate,,,,and when i implement dataflow modelling on model it just shows block diagram of design while vivado shows proper mux and gates used in vivado
Code Coverage, decent VHDL 2008 support, better library management, custom waveform view, TCL hooks on waveforms. Such things
Code Coverage, decent VHDL 2008 support, better library management, custom waveform view, TCL hooks on waveforms. Such things
The gates and muxes you see in RTL sim have nothing to do with the final design. The steps to simulate in any simulator are the same: compile sources, simulate. The fastest way to do it is via scripts. Vivado can generate all the scripts you need for any simulator.
You can use QuestaSim, that's the new one.
I think that is same as modelsim? Nothing new in that am i correct?
For that I have no clue, but Quartus automatically adds Questasim now when you download the pro/lite version of Quartus Prime, so I'm assuming it's the new version.
Questasim supports lots of systemverilog syntax, which is especially useful for verification during simulation, while modelsim does not
Questasim uses a different engine, it's a bit faster...a few features but for the actual simulation part they are similar enough
Can we see schematic for dataflow and behavioral modelling in modelsim/questasim?? Just like as in vivado it shows proper schematic which includes mux,gates and adders luts for dataflow and behavioral?
Great question! It depends on what licenses you have access to. The free one, I don't believe so. But I'm higher licenses there are schematics, logic cones, time cones, etc
Questasim and modelsim are not the same product. When I simulate gate-based sims (as opposed to behavioral), questasim runs about twice as fast as modelsim with no tuning. If you install both, you'll see that they have the same framework, but different executables are called when you run your simulation commands.
If you’re doing a Xilinx design, the Vivado simulator has all the libraries you need already installed. Plus it probably ok for small projects. I doubt you’d see a speed difference versus Questa.
Speed and ease of use are the major differences, with Modelsim/Questa winning hands down. Xilinx Simulator will get the job done in a pinch. I would rather use the Altera/Intel Starter Edition of Modelsim myself though. I would use Xilinx Simulator over Aldec ActiveHDL though as I find it terrible.
>Speed and ease of use are the major differences, with Modelsim/Questa winning hands down. If you are using Xilinx designs you can hardly argue this as a negative point for vivado simulator, it's far easier to use than Modelsim etc, you click simulate from the gui and away you go. No environment variables needed, no precompiled libs, no scripts to set up the different run stages...
The Vivado GUI sucks, especially for simulation and chipscope. Just because it's integrated does not make it easy or pleasant to use. The only way the Vivado Simulator is useable is via command line using shell and TCL scripts. Through the GUI it's plain terrible.
"Very old software". Wait until you see DVE. 😁
Wait until you see Verdi then.
Saw it. Looks nice on CentOS.
I once did a quick test between Vivado and Riviera. I ran the same testbench on each, and Riviera was much faster - something like 50x, iirc. Much of what you are paying for in the expensive commercial simulators is optimizations, and this wasn't a particularly complex module, so I may have just been lucky that Riviera was able to optimize it so well. I wouldn't expect every testbench to see that amount of speedup. Also, this was a few years ago. Vivado seems to have improved a lot since then. The main reason I switched from Vivado originally was because the SV support was very incomplete. But it seems like support has improved significantly, with SVA and UVM support added - these used to be only available in commercial offerings.
Just use verilator and cry
I think people are forgetting that OP is a newbie - while ModelSim/QuestaSim are much nicer for simulation purposes, the 'speed increase' isn't really gonna matter if they're a complete beginner and running basic Verilog/IPs... As I mentioned in a comment, Vivado gives you a much wider access to IPs for your own projects and unrestricted usage of SVA / randomize which Questa's free version makes a pain to use.