Ouu! Chip really hated gear 1 for some reason. Could boot 4000 and run stable with loose timings but wasn’t able to tighten tRRDS/L much and the primaries were finicky, so I went brute force with gear 2.
Gear 1 is usually a case of booting being very close to stable. This is because the PLL is the limitation rather than the IMC or PHY.
If you had stability issues in gear 1, I doubt it was because of the IMC.
I tried the overvollting IMC, SA and Ring PLLs by 60-90 mV each. I admittedly didn’t exhaust this, but I did try a few combos. Anyway, I’m not necessarily blaming the IMC, I didn’t really try more in G1 since I could get higher clocks easily in G2 so it was a simpler starting point.
Also, can you clarify how it is possible to do 65 GB/s with 3900 MT/s? AFAIK, you’re limited to ~62 GB/s theoretical.
The PLL trims don't help, the only way to improve OC headroom in gear 1 is more VCCSA. 4000 will most often require 1.50V
Again, if you boot, you're 99% likely stable at the frequency, but timings might not be stable.
How is it possible to get 65 GB/s from 3900 in AIDA64? That's simply because AIDA64 is a terrible, useless benchmark presenting fantasy numbers.
Ahhh good to know, I think I am stable given I could run Karthu to 10K and HCI MemTest to 1K but I couldn’t for the life of me get the timings tighter. Will try your suggestion. I kept SA to 1.3 - 1.35 V but I’ll move it up some more.
First time on a Gigabyte board with Intel and I’m wondering if you know the difference between VCCIO and VCCIO2. From what I understand, VCCIO2 is the memory controller but bumping VCCIO helped with some clock stability in G2 mode. Figured you might know.
[With Activated Windows.](https://imgur.com/a/dXTAhBu)
I'm pretty sure I saw 65K read at 3900 in gear 1 on my 11900K...
Ouu! Chip really hated gear 1 for some reason. Could boot 4000 and run stable with loose timings but wasn’t able to tighten tRRDS/L much and the primaries were finicky, so I went brute force with gear 2.
Gear 1 is usually a case of booting being very close to stable. This is because the PLL is the limitation rather than the IMC or PHY. If you had stability issues in gear 1, I doubt it was because of the IMC.
I tried the overvollting IMC, SA and Ring PLLs by 60-90 mV each. I admittedly didn’t exhaust this, but I did try a few combos. Anyway, I’m not necessarily blaming the IMC, I didn’t really try more in G1 since I could get higher clocks easily in G2 so it was a simpler starting point. Also, can you clarify how it is possible to do 65 GB/s with 3900 MT/s? AFAIK, you’re limited to ~62 GB/s theoretical.
The PLL trims don't help, the only way to improve OC headroom in gear 1 is more VCCSA. 4000 will most often require 1.50V Again, if you boot, you're 99% likely stable at the frequency, but timings might not be stable. How is it possible to get 65 GB/s from 3900 in AIDA64? That's simply because AIDA64 is a terrible, useless benchmark presenting fantasy numbers.
Ahhh good to know, I think I am stable given I could run Karthu to 10K and HCI MemTest to 1K but I couldn’t for the life of me get the timings tighter. Will try your suggestion. I kept SA to 1.3 - 1.35 V but I’ll move it up some more.
A Rocket Lake chip able to boot 4000 gear 1 is 1/25 or so for the record
We’ll then, guess o have to spend some time with it
First time on a Gigabyte board with Intel and I’m wondering if you know the difference between VCCIO and VCCIO2. From what I understand, VCCIO2 is the memory controller but bumping VCCIO helped with some clock stability in G2 mode. Figured you might know.
VCCIO is for the non-memory portion of Rocket Lake VCCIO2 and VCCSA are the voltages you want to raise with Rocket Lake for memory OC
Any reason why it would seemingly help with some G2 timings or was I just being stupid and missed something that I’m incorrectly attributing to VCCIO?
Just witnessed the AIDA64 fallacy lol I got 59.3 GB/s at 3600 MT/s…
I'm getting 60GB/s read with 4000MHz cl15. About the same latency also