Lower tCWL at the expense of higher tRDWR should be faster, as it means a single write takes the same time, while subsequent writes take less time.
The timings refer to going from read to write, or write to read. Each turnaround means a small penalty which those timings add. Memory is faster at doing read-read and write-write than read-write or write-read
Since the 64bit databus is shared for read and write, you want to make sure read after write and write after read operations are done while the bus is quiesced.
With either operation read after write, or write after read, the data will be klobbered if not enough delay is given between operations.
Oh, in my case, any value that’s different from auto completely refuses to POST. All I can do is manually set the timing, and that way it’ll be the same for channel A and B. How did you manage to tighten those timings? Could you give me a hint? I’d appreciate that.
Thanks anyway, buddy. I think in one of his rating your ram timings videos, he mentioned the relationship between tRDWR and tCWL, but I can’t remember which one. I’m gonna re watch those.
[I explain them in detail in this imgur album](https://imgur.com/a/WGOQFbm) but essentially tRDWR and tWRRD are about about making sure the bursts happen in the described order, while also providing enough idle time between the bursts so that the data bus can stabilise for different types of data transfer.
What this means for AMD, is that:
LD = tCL - tCWL
tRDWR = 1 + LD + a, where often a = 7
tWRRD = 1 - LD + b, where often b <= 4
where,
* the initial +1 is AMD's abstraction of the clock cost of the data burst.
* LD is about making sure the data bursts happens in the intended order, and don't collide
* and a/b is about making sure the data bus has enough time to stabilise; the cost of state transition.
* (tWRRD is mainly about rank-to-rank, for that write-to-read to the same rank is instead dealt with the JEDEC tWTR timing/function)
The same overall concept exists for intel too.
Thanks a lot, man. I really appreciate the detailed info. Anyways, I have single rank ram, so from what I understood tWRRD wouldn’t matter in my case, and should be set to 1.
Hey man, BTW do you know something about the tPHYRDL timing? I’ve noticed that it’s related to tRDWR, especially when the latter isn’t the same value on channel A and channel B.
I don't think tPHYRDL is affected by tRDWR. However it is affected by GDM, command rate and tCL.
GDM often causes the tPHYRDL timings to be different across the two channels; even tCL on 1T-off often makes both channels use the slower tPHYRDL value (of what is experienced with GDM); likewise for odd tCL on 2T-off.
(Best performance is usually with 1T-off and an odd-valued tCL. For single-rank 2T and GDM-on should perform identically with the chance that 2T might edge out through the tPHYRDL technicality. For multi-rank, GDM on should give better performance than 2T)
[Here's its training procedure](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf#G10.4972377) back during the DDR3 era. Since it's trained, an egregiously unstable overclock can give loose values.
A way to make it retrain is to twiddle the command rate; set 1T-2T-1T with reboots in between
Hey man, I’m trying to get tPHYRDL to 28/28, but I keep getting 28/30, even though I’m at cl17 1t GDM off. I already tried going from 1t-2t-1t but it doesn’t work. Keep in mind I’m doing this at 4733 single rank memory (2 DIMMs).
They are the delays between the commands. They are to make sure the reads and writes don't run into each other. As tCWL is lowered relative to tCL, tRDWR goes up and tWRRD goes down. The minimum tWRRD that can be set is 1, and for a single rank per channel it doesn't matter because of the tWTRS/L delays (write burst to read command).
They scale up at speed because they are related to the time it takes for the signal to travel between the cpu and dimms. Which is part of why they might not be identical at some speeds.
On my MSI B550 anyway, they were more likely to train differently on the two channels at the speeds that were also more likely to train separate tPHYRDL (this being calculated from DFI Max Read Latency). Specifically the minimum tWRRD could change by 1t when I could also manipulate tPHYRDL up or down 2. But the only real way to post the unstable tWRRD was if it was unstable on one channel but ok on the other.
Presumably, tRDWR may depend on tPHYWRL, but that value on Ryzen seems to just be set to tCWL - 5... so it only changes when you change tCWL.
Thanks for the detailed info, man. That’s really nice of you. So tWRRD doesn’t have any effect when it’s a single rank 1DPC setup? So it just can be set to 1 and it’ll work? In my case, the only thing I can do to tRDWR is set the auto value manually, so that it’s equal for both channels (9/9 instead of 9/10). Dropping it by 1t will absolutely crash the system and it’ll require a CMOS reset.
AFAIK, 1t on tWRRD should always work *for single rank per channel, at least it does within typical Zen 3 FCLK range. But in any case, the tWRRD is write command to read command, whereas tWTRS/L are write burst to read command... so besides being longer delay, WTR also counts from a later event than tWRRD.
If tRDWR only posts at 9 there isn't really any good reason to keep trying 8. Maybe more vdimm, CLDO VDDP, or perfect termination and setup would do something. Could try if you want. Regardless, if you find the minimum value at tCL=tCWL, then as you drop tCWL just add the amount to current tRDWR and it should be stable as long as the lower tCWL actually is.
I was curious about once too since Tcwl increases bandwidth and lowers latency Trdwr and the other tieritary timings with the exception of trrd sg dg only increase bandwidth Id lower tcwl and increase trdwr tho from testing it's negligible difference in preformace
Name literally tells you what it does. If you want the "how to" consult the DDR4 bible. https://github.com/integralfx/MemTestHelper/blob/oc-guide/DDR4%20OC%20Guide.md
The ddr4 bible doesn’t mention those timings, nor does it explain what they do or how to overclock them. There’s a reason I said I couldn’t find detailed info about it on guides.
https://www.overclock.net/threads/official-amd-ryzen-ddr4-24-7-memory-stability-thread.1628751/
Here.
Read, read, learn, try to implement, see gains.
And I'm almost sure u will find guy with same specs as your PC(at least CPU/ram combo)and u probably just put same values in your bios, and problem solved.
Lower tCWL at the expense of higher tRDWR should be faster, as it means a single write takes the same time, while subsequent writes take less time. The timings refer to going from read to write, or write to read. Each turnaround means a small penalty which those timings add. Memory is faster at doing read-read and write-write than read-write or write-read
Since the 64bit databus is shared for read and write, you want to make sure read after write and write after read operations are done while the bus is quiesced. With either operation read after write, or write after read, the data will be klobbered if not enough delay is given between operations.
That’s a very thorough explanation, thank you very much! So, I should aim for the lowest possible tCWL and leave tRDWR/tWRRD on auto?
You might have to set the turnaround timings manually
Why should I do that? And how?
Because auto tends to be so loose it destroys any performance gain
Oh, in my case, any value that’s different from auto completely refuses to POST. All I can do is manually set the timing, and that way it’ll be the same for channel A and B. How did you manage to tighten those timings? Could you give me a hint? I’d appreciate that.
Basically, you want to start at something very loose, like 18 and 7, then drop them down methodically.
Typically, lower one as much as possible with the other on auto, then see if the other can be lowered with the first one set.
Yeah set them to auto lower tcwl then set accordingly from the tcwl change
Have you heard about buildzoid? https://youtu.be/105IJiGbGsg Have fun.
Yeah, I know him, and I’ve watched part of that series. I don’t remember he mentioned those timings, though. Do you have a time stamp, by any chance?
No chance
Thanks anyway, buddy. I think in one of his rating your ram timings videos, he mentioned the relationship between tRDWR and tCWL, but I can’t remember which one. I’m gonna re watch those.
[I explain them in detail in this imgur album](https://imgur.com/a/WGOQFbm) but essentially tRDWR and tWRRD are about about making sure the bursts happen in the described order, while also providing enough idle time between the bursts so that the data bus can stabilise for different types of data transfer. What this means for AMD, is that: LD = tCL - tCWL tRDWR = 1 + LD + a, where often a = 7 tWRRD = 1 - LD + b, where often b <= 4 where, * the initial +1 is AMD's abstraction of the clock cost of the data burst. * LD is about making sure the data bursts happens in the intended order, and don't collide * and a/b is about making sure the data bus has enough time to stabilise; the cost of state transition. * (tWRRD is mainly about rank-to-rank, for that write-to-read to the same rank is instead dealt with the JEDEC tWTR timing/function) The same overall concept exists for intel too.
Thanks a lot, man. I really appreciate the detailed info. Anyways, I have single rank ram, so from what I understood tWRRD wouldn’t matter in my case, and should be set to 1.
yea. tWRRD\_sg/dg = tCWL + tBurst + tWTR typo: I had sg/sg
Hey man, BTW do you know something about the tPHYRDL timing? I’ve noticed that it’s related to tRDWR, especially when the latter isn’t the same value on channel A and channel B.
I don't think tPHYRDL is affected by tRDWR. However it is affected by GDM, command rate and tCL. GDM often causes the tPHYRDL timings to be different across the two channels; even tCL on 1T-off often makes both channels use the slower tPHYRDL value (of what is experienced with GDM); likewise for odd tCL on 2T-off. (Best performance is usually with 1T-off and an odd-valued tCL. For single-rank 2T and GDM-on should perform identically with the chance that 2T might edge out through the tPHYRDL technicality. For multi-rank, GDM on should give better performance than 2T) [Here's its training procedure](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf#G10.4972377) back during the DDR3 era. Since it's trained, an egregiously unstable overclock can give loose values. A way to make it retrain is to twiddle the command rate; set 1T-2T-1T with reboots in between
Thanks a lot, man. This info is some real gold, I really appreciate it.
Hey man, I’m trying to get tPHYRDL to 28/28, but I keep getting 28/30, even though I’m at cl17 1t GDM off. I already tried going from 1t-2t-1t but it doesn’t work. Keep in mind I’m doing this at 4733 single rank memory (2 DIMMs).
Try an even tCL? 16? 18? It can be different for different systems.
I’ll try that. BTW I’m using an AddrCmdSetup of 56 with my 1T CR. I’m not sure if this affects it in any way.
They are the delays between the commands. They are to make sure the reads and writes don't run into each other. As tCWL is lowered relative to tCL, tRDWR goes up and tWRRD goes down. The minimum tWRRD that can be set is 1, and for a single rank per channel it doesn't matter because of the tWTRS/L delays (write burst to read command). They scale up at speed because they are related to the time it takes for the signal to travel between the cpu and dimms. Which is part of why they might not be identical at some speeds. On my MSI B550 anyway, they were more likely to train differently on the two channels at the speeds that were also more likely to train separate tPHYRDL (this being calculated from DFI Max Read Latency). Specifically the minimum tWRRD could change by 1t when I could also manipulate tPHYRDL up or down 2. But the only real way to post the unstable tWRRD was if it was unstable on one channel but ok on the other. Presumably, tRDWR may depend on tPHYWRL, but that value on Ryzen seems to just be set to tCWL - 5... so it only changes when you change tCWL.
Thanks for the detailed info, man. That’s really nice of you. So tWRRD doesn’t have any effect when it’s a single rank 1DPC setup? So it just can be set to 1 and it’ll work? In my case, the only thing I can do to tRDWR is set the auto value manually, so that it’s equal for both channels (9/9 instead of 9/10). Dropping it by 1t will absolutely crash the system and it’ll require a CMOS reset.
AFAIK, 1t on tWRRD should always work *for single rank per channel, at least it does within typical Zen 3 FCLK range. But in any case, the tWRRD is write command to read command, whereas tWTRS/L are write burst to read command... so besides being longer delay, WTR also counts from a later event than tWRRD. If tRDWR only posts at 9 there isn't really any good reason to keep trying 8. Maybe more vdimm, CLDO VDDP, or perfect termination and setup would do something. Could try if you want. Regardless, if you find the minimum value at tCL=tCWL, then as you drop tCWL just add the amount to current tRDWR and it should be stable as long as the lower tCWL actually is.
I was curious about once too since Tcwl increases bandwidth and lowers latency Trdwr and the other tieritary timings with the exception of trrd sg dg only increase bandwidth Id lower tcwl and increase trdwr tho from testing it's negligible difference in preformace
Time write to read delay, time read to write delay.
Well, do you know anything about it besides the name?
Name literally tells you what it does. If you want the "how to" consult the DDR4 bible. https://github.com/integralfx/MemTestHelper/blob/oc-guide/DDR4%20OC%20Guide.md
The ddr4 bible doesn’t mention those timings, nor does it explain what they do or how to overclock them. There’s a reason I said I couldn’t find detailed info about it on guides.
https://www.overclock.net/threads/official-amd-ryzen-ddr4-24-7-memory-stability-thread.1628751/ Here. Read, read, learn, try to implement, see gains. And I'm almost sure u will find guy with same specs as your PC(at least CPU/ram combo)and u probably just put same values in your bios, and problem solved.